The phase locked loop (PLL) and frequency locked loop (FLL) are well-known closed loop feedback circuits commonly used to maintain synchronization between an oscillator or other clock or frequency signal generator, such as a digital frequency synthesizer, and a reference signal. FIG. 1 illustrates an embodiment of a typical prior art PLL. In the example shown, in PLL 100 the output of oscillator 102 is provided to a divider, the output of which is provided to a phase detector 106. The phase detector 106 receives a reference (e.g., timing) signal on line 108, and generates and provides as output on line 110 an error signal that reflects the difference in phase, if any, between the feedback signal provided by divider 104 and the reference signal received on line 108. The error signal on line 110 is filtered using a low pass filter 112 (sometimes referred to as a “loop filter”) to provide to oscillator 102 via line 114 a control signal to keep the oscillator in synch with the reference signal, e.g., by causing it to speed up or slow down—for example by increasing or decreasing the control voltage supplied to a voltage control oscillator—as required to bring it back into phase synchronization with the reference. A FLL is similar to a PLL except that the time derivative of the phase information is used.
A PPL or FLL achieve acceptable results and performance in environments in which the communication path between the source of the reference signal and the PLL or FLL is stable and/or predictable. However, if the transmission path is characterized by excessive jitter/noise and/or is susceptible to long term changes, such as long term changes in average transmission delay, such conditions can affect the results obtained by using a typical prior art PLL or FLL. One possible response to jitter or noise in the transmission path would be to narrow the bandwidth of the loop filter, to filter out the jitter or other noise. However, that approach has the potentially undesirable effect of significantly slowing response to conditions affecting oscillator performance, such as environmental changes (e.g., increased or decreased temperature), crystal or other oscillator component aging, and other factors that can affect the short term accuracy of an oscillator. A FLL typically would respond better than a PLL to long term changes in transmission delay of the reference/timing signal; however a typical prior art FLL suffers from the same shortcoming as a typical prior art PLL with respect to the effect of jitter or other short term noise in the transmission path.
Therefore, there is a need for an effective way to maintain synchronization between a local oscillator and a reference signal transmitted via a path characterized by excessive jitter or other noise. Similarly, there is a need for an effective way to maintain synchronization between a local oscillator and a reference signal when changes in the long term average transmission delay of a path via which the reference signal is provided.